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- 일시 : 2018년 5월 10일(목) 13:30

- 장소 : 공학관 457호

- 초청강사 : 장도영 박사 (IMEC, 벨기에)

제목 : Logic CMOS technology evolution and challenges for sub10nm node

[Abstract]

Over the past decades, in logic CMOS technology, the scaling is the most important keyword expecting power, performance, area, and cost benefits. For the successful scaling, several device innovations were introduced such as source/drain stressors and high-k dielectric/metal-gate process at sub-100nm node. At 22nm node, the FinFET replaced the conventional planar transistor finally by improving the channel control and high drive capability. In this talk, the recent technology scaling trend and challenges at device-level will be reviewed and various efforts on further technology scaling will be discussed in terms of design-enabled technology development.

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